Field of the Invention
Embodiments of the present invention generally relate to clock and data recovery (CDR) systems, and more particularly, to managing estimation and calibration of non-ideality of a Phase Interpolator (PI) in PI-based CDR system.
Description of the Related Art
In order to communicate data from a transmitter to a receiver across a signal line, the receiver must know when to sample the data signal that the receiver receives from the transmitter. In many systems, this information is provided by a timing (or clock) signal sent from the transmitter to the receiver along a dedicated timing (or clock) signal line adjacent to the data signal line.
In systems with relatively low signaling rates, the receiver can directly use an internally buffered version of a timing signal to extract the data from the data signal, as used in Synchronous dynamic random access memory (SDRAM) technology. In systems with higher signaling rates, however, the receiver typically requires a clock alignment circuit, such as a Phase Locked Loop (PLL) or Delay Locked Loop (DLL). The clock alignment circuits create an internal sampling clock signal, precisely aligned with the received timing signal, to extract the data from the data signal, as used in Dynamic RAM (DRAM) and Double data rate (DDR) technologies. Regardless of whether a clock alignment circuit is used, the data and timing lines must be well matched to eliminate timing skews between them which reduce a system's timing margin.
As data rates continue to increase, it is becoming increasingly difficult to match the data and timing signal lines to eliminate timing skews. Furthermore, requiring a timing signal line to be routed along with the data line(s) is costly in terms of board area and power. An attractive option is to remove the timing line and instead use a circuit on the receiver that requires only the data signal to determine when to sample the data signal to most reliably extract the data. The circuit is called a clock and data recovery (CDR) circuit.
Although CDRs are typically designed using a modified phase-locked loop (PLL), such PLL-based CDRs are difficult to design, costly in terms of power and area, and suffer from several other limitations. For example, in designing a PLL-based CDR, the designer must compromise between the ability to track the data signal and noise suppression of the PLL. Additionally, the dynamics of PLL-based CDRs are dependent on the contents of the data signal, and PLL-based CDRs can have a long locking time since they must lock to both the frequency and phase of the data signal. PLL-based CDRs also suffer from analog offsets and device mismatches, which can cause the receiver circuitry to sense the data signal at shifted, sub-optimal sampling points. Lastly, for receivers receiving multiple data signals, a dedicated PLL-based CDR must be provided for each data signal. Providing dedicated PLL-based CDR for each data signal is a costly requirement since the PLLs typically require relatively large silicon area (e.g. for large filter capacitors) and dissipate relatively large amounts of power (e.g. for various high speed PLL components).
In widely used serial communication, the data is transmitted from the transmitter to receiver without a synchronous clock. The received data suffers from asynchronous and noise effects. To recover the data, a system needs to extract a clock and use the extracted clock to synchronize and clear the data. The system is called clock and data recovery (CDR) system.
However, the received data accumulates jitter and noise during transmission. Thus, adjusting the phase of the recovery clock based on the received data is a chief function in the CDR system. In general, low bit-error-rate (BER) communication of data over a communications channel is often considered an important requirement in many systems. To recover the data correctly and decrease the BER, the extracted clock needs to track the phase of the received data timely and accurately.
The BER is a function of many parameters, including a phase of a clock signal or phases of clock signals. An incorrect phase or timing of a respective clock signal may reduce a timing margin and/or increase the BER. As a consequence, communications devices and systems often include components, such as phase locked loops (PLLs), delay locked loops (DLLs) and phase interpolators (PIs), that allow the phase of the respective clock signal to be adjusted. For example, a PI may generate the respective clock signal having the phase that corresponds to a control signal applied to the PI. The control signal may specify a phase step or setting.
PI is the most critical module in the CDR system. However, the PI suffers from non-linearity. The non-linearity of the PI directly affects the dynamic characteristic of the CDR system thereby leading to an error. While a frequency difference exists between the input data and the local clock, it also affects the jitter tolerance of the CDR system. Many of the timing problems related to high-speed signaling are mitigated through the use of phase-interpolating circuits to generate precise clock phases.
Unfortunately, there may be nonlinearities or errors in a mapping from the phase code or step to the phase of the respective clock signal. Resulting phase errors may adversely impact the device and/or system performance, as discussed above. As a consequence, testing of such nonlinearities (or the converse, timing linearity) is often included in the characterization and acceptance of devices, such as integrated circuits. This testing is often performed using dedicated, external test equipment. Such test equipment, however, is often expensive. The accuracy and/or repeatability of the test equipment may be insufficient. Testing for nonlinearities over a wide range of phase steps may be time consuming, thereby further increasing the expense.
Another problem is that the nonlinearities of PIs become unacceptably large in the presence of process variations and routing mismatches. The non-linearity errors result in inaccurate clock timing, and may go unnoticed in high volume manufacturing (HVM). The non-linearity errors result in wrong timing margining results or poor input/output (I/O) performance due to inaccurate timing training.
PI-based CDR circuits are commonly used in high speed serial I/O links to recover data signals that have become distorted due to noise or attenuation. In a typical data recovery circuit, three identical PI circuits are often used. Thus, in order to minimize the layout area, segmented PI circuits, consisting of two circuit stages, are often implemented to allow for high-resolution phase interpolation. However, the segmented PI circuit design has shown a high level of non-linearity during what is known as inter-quadrant switching. Specifically, some existing segmented PI circuits have shown 30 ps phase non-linearity during inter-quadrant switching, which is high when compared to a desirable step adjustment target of 6.6 ps. The high non-linearity caused by inter-quadrant switching has been shown to introduce a significant amount of jitter into the PI-based CDR circuit.
There is a need, therefore, for enhanced methods, apparatuses and systems for managing estimation and calibration of non-ideality or linearity of a PI-based CDR circuit.